About
I have 7.5+ yrs Experience as Senior Verification Engineer with a demonstrated history of working in the semiconductors industry. Have a strong verification skill like constraints-based Environment testing and debugging, for successful ASIC and FPGA Development. Developed a Test-bench architecture for sequences/Driver using System Verilog language Framework using (UVM-Universal Verification Methodology). Verilog/HDL, VHDL, C, C++.
I have extensive experience with various protocols such as AXI-3, AXI-4, I2C, I3C, SMBUS, AMBA-CHI5, PCIe, ETHERNET, and SPI. This diverse protocol exposure highlights his versatility in handling a wide range of projects and scenarios within the VLSI domain.
I have Strong communication, interpersonal, and presentation skills. A skilled communicator, able to synthesize and deliver complex information to diverse audiences. Creative, flexible, able to adapt to changing priorities and maintain a positive attitude and strong work ethic. A track record for meeting timelines and exceeding expectations.
Experience
present NOV 2022
Senior Verification lead L1
Client: NXP
Project: Mc-Lena Ethernet
- Handling a small teams of developers.
- TJA1104 (Mc-Lena) is 100 BASE-T1 Automotive Ethernet PHY.
- Mc-Lena is intended for system that need external 100 Base -T1 PHY.
- The product is built around Si-proven butterfly which is 100Base -T1 transceiver IP with Additional interface to support SGMII/XMII PHY Interface.
- Implementation of GLS from scratch.
- Debugging and fixed some failing tests.
- Perform Unit delay and timing delay gate level simulation for all required testcase with provided SDFs for SMGII, XMII and no- VIP, IP.
- Debugged Flop initialization issues and X propagation.
- Ethernet
- System Verilog
- UVM
- GLS(Gate Level Of Simulation)
- X-propagation
- Python
- Regression
OCT 2022 SEPT 2021
Senior Verification Engineer
Client: Intel
Project: WHS-HALK
- Understanding s3m bring up in WHS arc-based C test Development.
- S3M is independent IP used for IBL soft memory used for initial integration.
- SOC integration s3m using for soft memory for ACE lib “IBL_soft_mems” replace soft memory with HIP.
- Implementation for SMBUS testcase and debugging.
- Functional verification soc along with verifying intercommunication between the sub blocks.
- Implantation for SPI Flash test case
- Implement a checker for SPI flash
- GLS implementation
- PCIe Debugging a test case check the link up for gen 3 recovery CFG for PHY to MAC.
- I2C Debugging a Test Case.
- Inte x-propagation excluding incomplete test point and debug test case
- S3M
- System Verilog
- Python Script
- UVM
- I2C
- SMBUS
- SPI
- I3C
- PCIe
AUG 2021 DEC 2020
Senior Verification Engineer
Client: Cyient
Project: Ethernet 800 G
- Automatic FEC/CRC generation and monitoring/checking.
- Test case generation and checking (Directed, random and semi-random/constrained-random test cases).
- 100G lane round robin is followed on byte basis.
- Round Robin scheme on packet basis for 800G traffic.
- Integration &Testing, Fixing the bug and updating.
- Implementation test case for scoreboard.
- System Verilog
- Python Script
- UVM
- I2C
- Ethernet
NOV 2020 March 2019
Verification Engineer
Client: Boeing
Project: DO-254,777-x
- Development a scoreboard and Arbiter.
- Triggering Error or Fatal Error NVM throughDevelopment a scoreboard and Arbiter. VIP modification.
- Implantation testcase.
- Predictor and sequences development as per requirement.
- Develop Verification Test Case by reviewing requirement provided by client and file Problem Report.
- Verification of VHDL Design of client propriety interfaces used in design of PLDs.
- Maintain a documatation in a Doors for VCD and VPRD requirement.
- Worked on Code Coverage and modify the procedure to achieve required percentage of coverage.
- Review the Results of the Test and file the Problem Report for any conflicts found.
- Test Plan creation and finding a link Error updating.
- Review Lead of getting all the Test Procedure reviewed by Reviewer following the process mentioned under DO-254 standards Create prediction logic.
- System Verilog
- UVM
- Doors
- Regression
- VCD
- VPRD
- I2C
- IOSF
- ARINC-429
- CLDL
- AXI3
- Code Reviewer
- ADB
- IFDL
FEB 2019 NOV 2018
Verification Engineer
Client: Cadence
Project: Analog Discovery with hip Bord, FPGA
- Developing test bench. Understanding the architecture and developing test scenarios according to the verification plan.
- To build the tb for driver, sequencer and monitor, sequences.
- The Analog Discovery and the hip board create a 3 test through wave from Air pump, water pump, and led.
- Functional coverage analyzes through the coverage report make a 100 %.
- Debug high priority critical client issues for the project.
- The start digital discovery executing the project capturing the wave from different cycle time.
- Monitor debugs using developed test cases and report AHI report with wave from automated Generate.
- Validation process after completing the verification.
- System Verilog
- UVM
- Regression
- FPGA
July 2018 AUG 2017
Verification Engineer
Client: HoneyWell
Project: Wireless Monitor and Reciver
- As per the Requirement, preparing a verification plan, creates test-benches Environment.
- Understanding the architecture and developing test case scenarios according to the Blocks.
- Analyze a code coverage and create a “init file” exclusion the test case is not pass for 100 % coverage.
- To Build the test bench and writing the sequences.
- Implement a coverage and predictor as per a requirement.
- Designed and analyzed test bench environment and perform required modifications.
- Experience in system level and module / block level verification ARM based SOC.
- System Verilog
- UVM
- SOc
- AXI-3
- Perl
July 2017 JAN 2017
Verification Engineer
Client: Cisco
Project: SG300-52p-28p
- Understanding the architecture and developing test scenarios according to the verification plan.
- Write a Verification Environment generate a signal and stimulate through DUT.
- The consists of 3 different fields Header, data, FCS.
- DUT under the test Verification IP to a Signals and environment through the coverage.
- The simulation time Bed FCS and Good FCS Report Showing.
- The overall design, preparing a verification plan, creates test-benches, debug verification results.
- System Verilog
- UVM
- SOc
- AXI-3
- Perl
- SPI
June 2016 JAN 2016
Design Engineer
Client: Truechip
Project: USB-3.0
- As per the client Requirement or Specification implement a design.
- Synthesis tools can detect RAM designs in the HDL code.
- The design unit dynamically switches between read and write operations
- Filling and fixing the verification bugs.
- Debugged and trace back issues using Sim-Vision tool.
- Assigned to create test cases to verify the BUS and Interrupts.
- Verilog
- HDL
- Codecovarage
DEC 2016 JUNE 2015
Design Engineer
Client: Feature Electronic
Project: DDR3
- As per the client Requirement or Specification implement a design.
- Synthesis tools can detect RAM designs in the HDL code.
- The design unit dynamically switches between read and writes operations.
- Filling and fixing the verification bugs.
- Debugged and trace back issues using Sim-Vision tool.
- Assigned to create test cases to verify the BUS and Interrupts.
- Verilog
- HDL
- Codecovarage
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